View CS8151_332568.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Back
CS8151 5.0 V, 100 mA Low Dropout Linear Regulator with Watchdog, RESET, and Wake Up
The CS8151 is a precision 5.0 V, 100 mA micro-power voltage regulator with very low quiescent current (400 A typical at 200 A load). The 5.0 V output is accurate within 2% and supplies 100 mA of load current with a typical dropout voltage of 400 mV. Microprocessor control logic includes Watchdog, Wake Up and RESET. This unique combination of low quiescent current and full microprocessor control makes the CS8151 ideal for use in battery operated, microprocessor controlled equipment. The CS8151 Wake Up function brings the microprocessor out of Sleep mode. The microprocessor in turn, signals its Wake Up status back to the CS8151 by issuing a Watchdog signal. The Watchdog logic function monitors an input signal (WDI) from the microprocessor. The CS8151 responds to the falling edge of the Watchdog signal which it expects at least once during each wake-up period. When the correct Watchdog signal is received, a falling edge is issued on the wake-up signal line. RESET is independent of VIN and operates correctly to an output voltage as low as 1.0 V. A RESET signal is issued in any of three situations. During power up the RESET is held low until the output voltage is in regulation. During operation if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. And finally, a RESET signal is issued if the regulator does not receive a Watchdog signal within the Wake Up period. The RESET pulse width, Wake Up signal frequency, and Wake Up delay time are all set by one external capacitor CDelay. The regulator is protected against short circuit, over voltage, and thermal runaway conditions. The device can withstand 74 volt peak transients, making it suitable for use in automotive environments. Features * 5.0 V 2%/100 mA Output Voltage * Micropower Compatible Control Functions - Wake Up - Watchdog - RESET * Low Dropout Voltage: 400 mV @ 100 mA * Low Sleep Mode Quiescent Current (400 A Typ) * Protection Features - Thermal Shutdown - Short Circuit - 74 V Peak Transient Capability - Reverse Transient (-50 V) * Internally Fused Leads in DIP-16 and SO-16L Packages
(c) Semiconductor Components Industries, LLC, 2002
http://onsemi.com
TO-220 SEVEN LEAD T SUFFIX CASE 821E 7 1 TO-220 SEVEN LEAD TVA SUFFIX CASE 821J TO-220 SEVEN LEAD THA SUFFIX CASE 821H 1 7 D2PAK 7-PIN DPS SUFFIX CASE 936H 7 DIP-16 NF SUFFIX CASE 648 SO-16L DWF SUFFIX CASE 751G 1
1
1
16 1 16
ORDERING INFORMATION
Device CS8151YT7 CS8151YTVA7 CS8151YTHA7 CS8151YDPS7 CS8151YDPSR7 CS8151YNF16 CS8151YDWF16 CS8151YDWFR16 *7 Lead/Pin. Package TO-220* STRAIGHT TO-220* VERTICAL TO-220* HORIZONTAL D2PAK* D2PAK* DIP-16 SO-16L SO-16L Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 750 Tape & Reel 25 Units/Rail 47 Units/Rail 1000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 9 of this data sheet.
1
March, 2002 - Rev. 10
Publication Order Number: CS8151/D
CS8151
PIN CONNECTIONS
TO-220 SEVEN LEAD
DIP-16 1 NC Tab = GND Pin 1. VOUT 2. VIN 3. WDI 4. GND 5. Wake Up 6. RESET 7. Delay NC NC GND GND NC Sense VOUT 16 Delay RESET Wake Up GND GND WDI NC VIN NC NC NC GND GND GND Sense VOUT 1
SO-16L 16 Delay RESET Wake Up GND GND WDI NC VIN
1 D2PAK 7-PIN
1
VOUT VIN Current Source (Circuit Bias) Overvoltage Shutdown VOUT Current Limit Sense
Internally connected on TO-220 and D2PAK
Wake Up
Delay
Timing Circuit
Wake Up Circuit
Sense
+- Thermal Shutdown
Error Amplifier
WDI Falling Edge Detector VOUT
Watchdog Circuit
Bandgap Reference
RESET RESET Circuit GND
Figure 1. Block Diagram
http://onsemi.com
2
CS8151
MAXIMUM RATINGS*
Rating Power Dissipation Output Current (VOUT, RESET, Wake Up) Reverse Battery Peak Transient Voltage (60 V Load Dump @ VIN = 14 V) Maximum Negative Transient (t < 2.0 ms) ESD Susceptibility (Human Body Model) ESD Susceptibility (Machine Model) Logic Inputs/Outputs Storage Temperature Range Lead Temperature Soldering Wave Solder (through hole styles only) Note 1 Reflow (SMD styles only) Note 2 Value Internally Limited Internally Limited -15 +74 -50 2.0 200 -0.3 to +6.0 -55 to +150 260 peak 230 peak Unit - - V V V kV V V C C C
1. 10 seconds max. 2. 60 seconds max above 183C *The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (-40C TA 125C, -40C TJ 150C, 6.0 V VIN 26 V,
100 A IOUT 100 mA, C2 = 47 F (ESR < 8.0 ), CDelay = 0.1 F; unless otherwise specified.) Characteristic Output Section Output Voltage, VOUT Dropout Voltage (VIN - VOUT) Load Regulation Line Regulation Ripple Rejection Current Limit Thermal Shutdown Overvoltage Shutdown Quiescent Current VOUT < 1.0 V IOUT = 200 A (Sleep) IOUT = 50 mA IOUT = 100 mA (Wake Up) VOUT = 5.0 V, VIN = 0 V 9.0 V < VIN < 16 V 6.0 V < VIN < 26 V, 0 < IOUT < 100 mA IOUT = 100 mA IOUT = 100 A VIN = 14 V, 100 A < IOUT < 100 mA IOUT = 1.0 mA, 6.0 V < VIN < 26 V 7.0 V < VIN < 17 V @ f = 120 Hz, IOUT = 100 mA VOUT = 4.5 V - 4.90 4.85 - - - - 60 100 150 50 - - - - 5.0 5.0 400 100 10 10 75 250 180 56 0.4 4.0 12 1.0 5.10 5.15 600 150 50 50 - - 210 62 0.75 - 20 1.5 V V mV mV mV mV dB mA C V mA mA mA mA Test Conditions Min Typ Max Unit
Reverse Current RESET Threshold High (RTH) Threshold Low (RTL) Hysteresis Output Low Output High Current Limit Delay Time
RTH VOUT Increasing RTL VOUT Decreasing RTH - RTL 1.0 V < VOUT RTL, IOUT = 25 A IOUT = 25 A, VOUT > RTH RESET = 0 V, VOUT > VRTH (Sourcing) RESET = 5.0 V, VOUT > 1.0 V (Sinking) POR Mode
VOUT - 0.3 4.5 150 - 3.8 0.025 0.1 3.0
- 4.7 200 0.2 4.2 0.5 12 5.0
VOUT - 0.04 4.91 250 0.8 5.1 1.30 80 7.0
V V mV V V mA mA ms
http://onsemi.com
3
CS8151
ELECTRICAL CHARACTERISTICS (continued) (-40C TA 125C, -40C TJ 150C, 6.0 V VIN 26 V,
100 A IOUT 100 mA, C2 = 47 F (ESR < 8.0 ), CDelay = 0.1 F; unless otherwise specified.) Characteristic Watchdog Input Threshold High Threshold Low Hysteresis Input Current Pulse Width 0 < WDI < 6.0 V 50% WDI Falling Edge to 50% WDI Rising Edge and 50% WDI Rising Edge to 50% WDI Falling Edge (see Figures 2, 3, and 4) - - - - 0.8 25 -10 5.0 1.4 1.3 100 0 - 2.0 - - +10 - V V mV A s Test Conditions Min Typ Max Unit
Wake Up Output Wake Up Period Wake Up Duty Cycle Nominal RESET High to Wake Up Rising Delay Time Wake Up Response to Watchdog Input Wake Up Response to RESET See Figure 2. See Figure 4. 50% RESET Rising Edge to 50% Wake Up Edge (see Figures 2, 3, and 4 ) 50% WDI Falling Edge to 50% Wake Up Falling Edge 50% RESET Falling Edge to 50% Wake Up Falling Edge, VOUT = 5.0 V 4.5 V IOUT = 25 A (Sinking) IOUT = 25 A (Sourcing) Wake Up = 5.0 V Wake Up = 0 V 30 40 15 40 50 20 50 60 25 ms % ms
- -
2.0 2.0
10 10
s s
Output Low Output High Current Limit
- 3.8 0.025 0.5
0.2 4.2 1.0 -
0.8 5.1 7.0 3.5
V V mA mA
PACKAGE PIN DESCRIPTION
PACKAGE PIN # TO-220 & 1 2 3 4 5 D2PAK DIP-16 8 9 11 4, 5, 12, 13 14 SO-16L 8 9 11 4, 5, 6, 12, 13* 14 PIN SYMBOL VOUT VIN WDI GND Wake Up FUNCTION Regulated output voltage 5.0 V 2%. Supply voltage to the IC. CMOS/TTL compatible input lead. The Watchdog function monitors the falling edge of the incoming signal. Ground connection. CMOS/TTL compatible output consisting of a continuously generated signal used to Wake Up the microprocessor from sleep mode. CMOS/TTL compatible output lead RESET goes low whenever VOUT drops by more than 6.0% from nominal, or during the absence of a correct watchdog signal. Input lead from timing capacitor for RESET and Wake Up signal. Kelvin connection which allows remote sensing of the output voltage for improved regulation. If remote sensing is not required, connect to VOUT.
6
15
15
RESET
7 -
16 7
16 7
Delay Sense
*Pin 6 GND is not directly shorted to the fused paddle GND. The fused paddle GND (pins 4, 5, 12, 13) is connected through the substrate. Pin 6 must be electrically connected to at least one of the fused paddle GND's on the PC board.
http://onsemi.com
4
CS8151
TIMING DIAGRAMS
VIN
RESET
Wake Up Duty Cycle = 50%
Wake Up
WDI
VOUT POR RESET High to Wake Up Delay Time Power Up Sleep Mode Normal Operation with Varying Watchdog Signal
Figure 2. Power Up, Sleep Mode and Normal Operation
VIN RESET Wake Up WDI
RESET Delay Time
VOUT POR RESET High to Wake Up Delay Time Wake Up Period RESET High to Wake Up Delay Time
Figure 3. Error Condition: Watchdog Remains Low and a RESET Is Issued
RESET Wake Up
Wake Up Period
WDI RTL VOUT Watchdog Pulse Width POR Watchdog Pulse Width Power Down POR
Figure 4. Power Down and Restart Sequence
http://onsemi.com
5
CS8151
DEFINITION OF TERMS Dropout Voltage: The input-output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100mV from the nominal value obtained at 14V input, dropout voltage is dependent upon load current and junction temperature. Input Voltage: The DC voltage applied to the input terminals with respect to ground. Line Regulation: The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected. Load Regulation: The change in output voltage for a change in load current at constant chip temperature. Quiescent Current: The part of the positive input current that does not contribute to the positive load current. The regulator ground lead current. Ripple Rejection: The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage. Current Limit: Peak current that can be delivered to the output.
CIRCUIT DESCRIPTION
Functional Description
To reduce the drain on the battery a system can go into a low current consumption mode when ever its not performing a main routine. The Wake Up signal is generated continuously and is used to interrupt a microcontroller that is in sleep mode. The nominal output is a 5.0 volt square wave with a duty cycle of 50% at a frequency that is determined by a timing capacitor, CDelay. When the microprocessor receives a rising edge from the Wake Up output, it must issue a watchdog pulse and check its inputs to decide if it should resume normal operations or remain in the sleep mode.
Wake Up WDI
Wake Up Response to WDI
Figure 5. Wake Up Response to WDI
RESET
The first falling edge of the watchdog signal causes the Wake Up to go low within 2.0 s (typ) and remain low until the next Wake Up cycle (see Figure 5). Other watchdog pulses received within the same cycle are ignored (Figures 2, 3, and 4). During power up, RESET is held low until the output voltage is in regulation. During operation, if the output voltage shifts below the regulation limits, the RESET toggles low and remains low until proper output voltage regulation is restored. After the RESET delay, RESET returns high. The Watchdog circuitry continuously monitors the input watchdog signal (WDI) from the microprocessor. The absence of a falling edge on the Watchdog input during one Wake Up cycle will cause a RESET pulse to occur at the end of the Wake Up cycle (see Figure 3). The Wake Up output is pulled low during a RESET regardless of the cause of the RESET. After the RESET returns high, the Wake Up cycle begins again (see Figure 3). The RESET pulse width, Wake Up signal frequency and RESET high to Wake Up delay time are all set by one external capacitor CDelay. Wake Up Period = (4 x 105)CDelay RESET Delay Time = (5 x 104)CDelay RESET High to Wake Up Delay Time = (2 x 105)CDelay Capacitor temperature coefficient and tolerance as well as the tolerance of the CS8151 must be taken into account in order to get the correct system tolerance for each parameter.
Wake Up
Wake Up Response to RESET
Figure 6. Wake Up Response to RESET (Low Voltage)
http://onsemi.com
6
CS8151
APPLICATION NOTES
Output Stage Protection
The output stage is protected against overvoltage, short circuit and thermal runaway conditions (see Figure 7). If the input voltage rises above the overvoltage shutdown threshold (e.g. load dump), the output shuts down. This response protects the internal circuitry and enables the IC to survive unexpected voltage transients. Should the junction temperature of the power device exceed 180C (typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.
> 50 V VIN VOUT
IOUT
Load Dump
Short Circuit
Thermal Shutdown
Figure 7. Typical Circuit Waveforms for Output Stage Protection Stability Considerations
The output or compensation capacitor C2 (see Figure 8) helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability.
VIN VOUT C1* 0.1 F CS8151 RESET RRST C2** 10 F
*C1 required if regulator is located far from the power supply filter. **C2 required for stability.
Figure 8. Test and Application Circuit Showing Output Compensation
The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provide this information. The value for the output capacitor C2 shown in the test and applications circuit should work for most applications, however it is not necessarily the optimized solution. To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low
http://onsemi.com
7
CS8151
temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.
Calculating Power Dissipation In a Single Output Linear Regulator
The maximum power dissipation for a single output regulator (Figure 9) is:
PD(max) + (VIN(max) * VOUT(min))IOUT(max) ) VIN(max)IQ
(1)
In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.
Heat Sinks
where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RJA can be calculated:
RQJA + 150C * TA PD
(2)
Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RJA:
RQJA + RQJC ) RQCS ) RQSA
(3)
The value of RJA can then be compared with those in the package section of the data sheet. Those packages with RJA's less than the calculated value in equation 2 will keep the die temperature below 150C.
IIN VIN IOUT SMART REGULATOR(R) VOUT
where: RJC = the junction-to-case thermal resistance, RCS = the case-to-heatsink thermal resistance, and RSA = the heatsink-to-ambient thermal resistance. RJC appears in the package section of the data sheet. Like RJA, it too is a function of package type. RCS and RSA are functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers.
} Control Features
IQ
Figure 9. Single Output Regulator with Key Performance Parameters Labeled
Battery VIN C1 CS8151 WDI VOUT C2 Microprocessor I/O VCC
CDelay CDelay GND
RESET
RESET
Wake Up I/O
Figure 10. Application Diagram
http://onsemi.com
8
CS8151
MARKING DIAGRAMS
TO-220 SEVEN LEAD T SUFFIX CASE 821E TO-220 SEVEN LEAD TVA SUFFIX CASE 821J TO-220 SEVEN LEAD THA SUFFIX CASE 821H D2PAK 7-PIN DPS SUFFIX CASE 936H 16 CS8151 AWLYWW
CS8151 AWLYWW CS8151 AWLYWW CS8151 AWLYWW
DIP-16 NF SUFFIX CASE 648 16 CS8151 AWLYYWW 1
SO-16L DWF SUFFIX CASE 751G
CS8151 AWLYYWW
1 1 1 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
1
PACKAGE DIMENSIONS
TO-220 SEVEN LEAD T SUFFIX CASE 821E-04 ISSUE C
Q A G B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.003 (0.076) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. INCHES MIN MAX 0.600 0.610 0.386 0.403 0.170 0.180 0.028 0.037 0.045 0.055 0.088 0.102 0.018 0.026 1.028 1.042 0.355 0.365 5 _ NOM 0.142 0.148 0.490 0.501 0.045 0.055 MILLIMETERS MIN MAX 15.24 15.49 9.80 10.23 4.32 4.56 0.71 0.94 1.15 1.39 2.24 2.59 0.46 0.66 26.11 26.47 9.02 9.27 5 _ NOM 3.61 3.75 12.45 12.72 1.15 1.39
L U K
OPTIONAL CHAMFER
D
M M
SEATING PLANE
C V M J
H M
DIM A B C D G H J K L M Q U V
http://onsemi.com
9
CS8151
TO-220 SEVEN LEAD TVA SUFFIX CASE 821J-02 ISSUE A
C -Q- B E
-T-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.540 0.555 0.050 BSC 0.570 0.595 0.014 0.022 0.785 0.800 0.322 0.337 0.073 0.088 0.090 0.115 0.146 0.156 0.289 0.304 0.164 0.179 0.460 0.475 3 MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 13.72 14.10 1.27 BSC 14.48 15.11 0.36 0.56 19.94 20.32 8.18 8.56 1.85 2.24 2.28 2.91 3.70 3.95 7.34 7.72 4.17 4.55 11.68 12.07 3
W U A HF L K M
D 0.356 (0.014)
M
7 PL
TQ
M
N S G J R
DIM A B C D E F G H J K L M N Q R S U W
TO-220 SEVEN LEAD THA SUFFIX CASE 821H-02 ISSUE A
-T- C -Q- B E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. 1. LEADS MAINTAIN A RIGHT ANGLE WITH RESPECT TO THE PACKAGE BODY TO WITH $0.020". DIM A B C D E F G J K L M N Q S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.023 0.037 0.045 0.055 0.568 0.583 0.050 BSC 0.015 0.022 0.728 0.743 0.322 0.337 0.101 0.116 0.090 0.115 0.146 0.156 0.150 0.200 0.460 0.475 3 MILLIMETERS MIN MAX 14.22 14.99 9.77 10.54 4.06 4.82 0.58 0.94 1.14 1.40 14.43 14.81 1.27 BSC 0.38 0.56 18.49 18.87 8.18 8.56 2.57 2.95 2.28 2.91 3.70 3.95 3.81 5.08 11.68 12.07 3
W U A L F K
M
D 0.356 (0.014)
M
7 PL
J
M
TQ
G
N
S
http://onsemi.com
10
CS8151
D2PAK 7-PIN DPS SUFFIX CASE 936H-01 ISSUE O
-T- SEATING PLANE B 8 V A 1 2 34 5 6 7 K F G D
7 PL M DIM A B C D E F G H J K M N U V NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS B AND M. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAX. INCHES MIN MAX 0.326 0.336 0.396 0.406 0.170 0.180 0.026 0.036 0.045 0.055 0.058 0.078 0.050 BSC 0.100 0.110 0.018 0.025 0.204 0.214 0.055 0.066 0.000 0.004 0.256 REF 0.305 REF MILLIMETERS MIN MAX 8.28 8.53 10.05 10.31 4.31 4.57 0.66 0.91 1.14 1.40 1.41 1.98 1.27 BSC 2.54 2.79 0.46 0.64 5.18 5.44 1.40 1.68 0.00 0.10 6.50 REF 7.75 REF
M
C E
U
H J
0.13 (0.005)
TB
M
N
DIP-16 NF SUFFIX CASE 648-08 ISSUE R
-A-
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
B
1 8
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
http://onsemi.com
11
CS8151
SO-16L DWF SUFFIX CASE 751G-03 ISSUE B
D
16 M 9
A
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 10.15 10.45 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
B
1 16X
8
B TA
S
B B
S
0.25
M
A
h X 45_
SEATING PLANE
M
8X
0.25
E
A1
14X
e
T
C
PACKAGE THERMAL DATA Parameter RJC RJA Typical Typical TO-220 7 LEAD 1.8 50 D2PAK 7-Pin 1.8 10-50* DIP-16 15 50 SO-16L 18 75 Unit C/W C/W
*Depending on thermal properties of substrate. RJA = RJC + RCA.
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC.
ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
L
http://onsemi.com
12
CS8151/D

▲Up To Search▲

Price & Availability of CS8151

	To Download CS8151 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .